Which of the following is true about the behaviour of a D Flip-Flop when the clock input is NOT transitioning?

Question

Question

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RRB JE CBT 2 (Electronics Engineering) ReExam Official Paper (Held On: 04 Jun, 2025)

Answer 1

The correct statement about the behavior of a D Flip-Flop when the clock input is NOT transitioning is: 1) The output remains at the last value.

Explanation:

Edge-Triggered Behavior: A D flip-flop is an edge-triggered device. This means it samples its input (D) and updates its output (Q) only at a specific transition of the clock signal (either the rising edge or the falling edge, depending on its design).
Latched State: When the clock input is not transitioning (i.e., it's held high, held low, or in between edges), the flip-flop is in a latched state. In this state, its output is isolated from the D input. Any changes in the D input during this period will not affect the output. The output simply holds the data that was present at the last active clock edge.